1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof, more specifically to a semiconductor device provided with a protection circuit or element suitable for a high speed and low power consumption type LSI (large scale integrated circuit), and a manufacturing method of such semiconductor device.
2. Description of the Related Art
An LSI provided with an MOS (metal oxide semiconductor) device has become very popular. The LSI includes an internal circuit constituted of a CPU (central processing unit), memory circuit, etc. and an I/O (input/output) port for external interface disposed around the internal circuit.
FIG. 18 shows apart of an internal circuit of a conventional LSI. The internal circuit 1 of the LSI constitutes a hybrid circuit consisting of two types of transistor (Tr) groups, namely LTr2 and MTr3. An objective of providing the LTr2 and MTr3 together is to satisfy the both requirements of higher processing speed and lower power consumption at a same time.
The LTr2 and MTr3 in the internal circuit 1 are operated under a same operating voltage while a threshold voltage Vt of the LTr2 is set higher and that of the MTr3 lower, therefore the LTr2 has a slow processing speed but consumes less power while the MTr3 has a high processing speed but consumes more power. Gate dielectric layers of the transistors constituting the LTr2 and MTr3, for each of which a threshold voltage is independently set, have a different film thickness, for example the film thickness of the LTr2 transistor is approx. 2.6 nm while that of the MTr3 transistor is approx. 1.9 nm.
The LSI provided with such the MOS device needs to include a power source protection circuit which serves to prevent a breakdown of a dielectric layer of the MOS device, since the gate dielectric layer is not resistant to an over current and easily breaks once an over current runs through it. This is because, ever since multi-oxide process was adopted in the manufacturing process aiming at a higher processing speed and lower power consumption by an LSI, as the gate dielectric layer has become thinner a breakdown voltage of the gate dielectric layer has lowered accordingly, from approx. 10V at a film thickness of approx. 8.0 nm to approx. 5V to 7V at a thickness of approx. 3.0 nm.
The power source protection circuit 4 to be incorporated in the internal circuit 1 of the LSI can be constituted of, for example, an N-channel transistor of a diode connection type.
As for the hybrid circuit as shown in FIG. 1, the power source protection circuit 4 needs to have functions to protect the MTr3 which has thinner gate dielectric layer and has a lower breakdown voltage. In addition to the above functions, the power source protection circuit 4 should be designed to reduce leak or off current therefrom especially when it is adopted to a low-consumption type LSI that is popularly used in a portable apparatus in order to reduce energy consumption.
Under the current circumstances in which the issue of the leak current and breakdown voltage has become more critical, increasing the leak current incurs so significant inconvenience that it is difficult to satisfy the both aspects of the leak current and the breakdown voltage.